1. Field of the Invention
The invention relates to multi-format active matrix displays, and multi-format devices for use therewith.
2. Description of the Related Art
The invention provides multi-format data drivers for controlling active matrix displays. The circuits of the drivers may be implemented in discreet driver integrated circuits, connected to the active matrix by direct bonding or via flexible circuit connections. In these cases, the circuits are almost always fabricated from crystalline silicon. Alternatively, the circuits may be integrated on the same substrates as the active matrix devices using the same processing steps. Devices of this type include thin film transistors (TFTs), in particular low and high temperature poly-silicon transistors. The invention is directly applicable to displays of portable equipment where data may be supplied to the display in a variety of formats and where display power consumption must be minimised.
FIG. 1 shows a typical active matrix liquid crystal (LC) display 2 composed of N rows and M columns of pixels. The boxes at the periphery of the active matrix represent the display driver electronics. It is the combined function of the digital data line driver 4 and scan line driver 6 to provide analogue data voltages to the electrodes 8 of the LC pixels from a digital image data source.
The digital data driver 4 typically receives image data from an LC controller integrated circuit (not shown). In addition to the image data, the driver 4 also receives control and timing signals such as a clock signal, and frame and line synchronisation signals. Image data is normally transmitted to the digital data driver 4 a line at a time, with each line corresponding to the required display states of a horizontal line of pixels of the display. The digital data driver 4 contains an array of input registers 10, as shown in FIG. 1. As a line of image data is transmitted to the driver 4, each data element is read into one of the input registers 10. The sampling pulses that activate the input registers 10 are generated by the timing generator 12. Once the entire line of image data has been sampled by the input registers 10, the data is transferred to an array of storage registers 16. During the time that the next line of image data is being transmitted to the driver 4, the data in the storage registers 16 is supplied to digital-to-analogue converter circuits 18.
The digital-to-analogue conversion operation may be non-linear such that it, compensates for the liquid crystal voltage/light-transmission characteristics. This transformation is known as gamma correction. Alternatively, the LC controller (not shown) may support gamma correction, in which case the digital-to-analogue conversion within the digital data driver 4 is a linear operation. The outputs of the converters 18 charge the source lines 20 (i.e. data lines) of the active matrix, and the scan driver 6 controls which row of pixels is charged from the source lines 20 through the pixel TFTs 22.
FIG. 2 shows a graph of light transmission plotted against electrode voltage for a typical twisted nematic liquid crystal pixel. Gamma correction for liquid crystal active matrix displays involves compensating for the pixel non-linear input voltage/light modulation characteristic. In order to annul the non-linearity such that equal changes in digital input correspond to equal changes in light transmission, a conversion circuit must implement the precise inverse of the function shown in FIG. 2. This inverse function is shown as the dashed line in the graph of FIG. 3. Along the x-axis is the digital input (6 bits shown in this example), and the y-axis indicates the analogue voltage required from the output of the digital-to-analogue converter.
There are two main strategies for implementing gamma correction. The first, shown in FIG. 4(a), involves a purely digital transformation. A RAM or ROM circuit 24 takes a digital input having (n+m) bits and generates an output which may have a greater number of bits than the input to preserve accuracy. These bits reflect the desired inverse function such that when they are supplied to a connected linear digital-to-analogue converter 26, the analogue output has the desired response to the input.
The second strategy involves gamma correction with a non-linear two-stage digital-to-analogue converter 28, as depicted in FIG. 4(b). This means of gamma correction is discussed in more detail below.
In FIG. 4(b), the digital-to-analogue converter (DAC) 28 is composed of two stages. A first stage DAC 30 receives the m most significant bits (MSBs) of the input, and a second stage DAC 32 receives the n least significant bits (LSBs). Reference voltages VR corresponding to each of the digital inputs from 0 to 2m are supplied to the first stage DAC 30. These reference voltages are represented by VR (0:2m) in FIG. 4(b). The MSBs are decoded in the first stage by the in bit to 2m line decoder 30 and the result is used to select which two of the 2m+1 gamma correction reference voltages, VR(0:2m), are supplied to the second stage DAC 32 of the converter 28. The two reference voltages VR supplied to the second stage DAC 32 are the VL and VH voltages indicated in FIG. 4(b).
Within the second stage DAC 32, the n LSBs are used to perform a linear digital-to-analogue conversion within the limits defined by VL and VH. The second stage digital-to-analogue converter 32 is typically built from capacitors or resistors, and switches. Because the capacitance of the video or source line load is usually high, a buffer circuit 34 is normally employed at the output of the circuit. The slew rate and settling time of the buffer then defines the minimum conversion time required to obtain a desired bit accuracy. The slew rate is the maximum rate of change of the output voltage of a buffer, and has units of V/s.
In the graph of FIG. 3, an example is shown of a 6 bit conversion afforded by such a converter circuit. In this particular example n=3 and m=3. The solid line shows that the actual output is a piecewise linear approximation to the desired output (the dotted line), with the gamma correction reference voltages defining the end-points of the linear element pieces.
FIG. 5 shows a known improved two-stage non-linear digital-to-analogue converter 36 which operates with a smaller conversion time (see British Patent Application No. 0011015.5). In comparison to FIG. 4(b), the improved circuit contains two switches which operate on non-overlapping clock phases, "PHgr"1 and "PHgr"2 (shown in FIG. 6). The first switch 38 denoted the precharge switch, allows the selected reference voltage VL to directly charge the output load 40 on phase "PHgr"1. The second switch 42, called the isolation switch, is open during the "PHgr"1 period so that the buffer output is isolated from the load 40. Because VL is a reference supply, the load is quickly charged to within n bits of its final desired value with a time constant defined by the pre-charge switch resistance and the load capacitance.
During "PHgr"2, the precharge switch 38 is open, and the buffer 34 applies the (m+n) bit analogue result from the digital-to-digital converter 36 to the load 40. At this moment, the load 40 has already been charged to within n bits of its final desired value, therefore the buffer output can reach this target much more quickly. A comparison of conversion times between this circuit and the one of FIG. 4(b) is shown in FIG. 6, in which the top and bottom graphs show the voltage outputs of the circuits of FIGS. 4(b) and 5 respectively.
The design of the sampling circuits in the input registers 10 and storage registers 16 of FIG. 1 may vary considerably depending on integration process technology. This is because the supply voltage for the sampling circuits is a process dependent factor, whereas it is desirable from power consumption considerations that the digital input and control signals are low voltage logic, for example a logic low of 0.0 V and a logic high of between 1.0 V and 5.0 V.
In the case of crystalline silicon integrated circuit drivers, where the supply voltage is the same as the logic input levels, the design of the sampling circuits is simpler, for example standard D-type latches or flip-flops may be used. For the case of poly-silicon (or other TFT) integrated drivers, the higher device threshold voltages may warrant a supply voltage that is significantly higher than the input logic levels for example vdd may be anywhere between 5.0 V and 15.0 V. The voltage disparity between input and supply means that voltage level is shifting is required within the sampling circuit.
FIG. 7 shows a prior art sampling circuit 42 (see British Patent Application No. 0005985.7) suitable for sampling an input logic signal (labelled INPUT in the schematic) that is significantly lower than the supply voltage, vdd. When the SAMPLE control signal is high (vdd), the output (denoted OUTPUT) is a level shifted logic equivalent of the input, signal. When the SAMPLE control signal is low (vss), the output is latched. The circuit 42 can be divided into two sub-circuits; a level-shifting sub-circuit constructed with devices M3 to M7, and a latching sub-circuit composed of devices M8 to M13.
The level shifting sub-circuit is activated when SAMPLE is high., P-type devices M4 and M6 are turned on, and N-type device M3 is turned off. Transistors M4 and M5, connected in series between vdd and a reference voltage, vref (which may be vss), together generate a bias voltage at the gate of transistor M7. Device M7 is configured as a common gate amplifier in which its source terminal is the input and its drain terminal, connected to load device M6, is the output. With careful device scaling and selection of vref, the output is a level-shifted logic equivalent of the input, which swings almost to the supply rails. The latching sub-circuit is activated when SAMPLE is low (devices M8 and M11 are turned on), and the logic state of the output is stored by crossed-coupled inverters M9/M10 and M12/M13.
During operation, only one of the sub-circuits is activated and controls the state of the output node, and the other is deactivated. When the level-shifting sub-circuit is activated, i.e. when SAMPLE is high, it is important to note that the power consumption of the circuit is at its highest. This is attributed to the currents flowing between vdd and vref (through M4 and M5) and between vdd and INPUT (through M6 and M7).
On screen display functions are typically used to overlay video data with simple text or graphical information. An example might be the display brightness setting of a digital camera which, when selected, is seen superimposed on the camera image provided from the CCD. This functionality is normally provided by an LC controller integrated circuit, such as the general purpose version shown in FIG. 8. This xe2x80x98chipxe2x80x99 can take input video data in either luminance and chrominance format or RGB formats and supplies either analogue or digital gamma-corrected RGB to the LC data drivers of an active matrix display. Any on-screen display data, supplied by the SRAM memory 44, is used to overwrite the video data in the display mixer circuit 46 shown. The present invention allows this function to be moved conveniently to the LC data driver circuit(s).
According to the invention there is provided a multi-format sampling register, digital to analogue converter, data driver and active matrix display as set out in the accompanying claims.
Format control signals are used to ensure that only those components are activated which are required for a given format, thus achieving a reduction in power consumption.